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m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 1. 2. preliminary this document is a preliminary target spec. and some of the contents are subject to change without notice. # 70-pin,400-mil tsop (type ii ) with 0.65mm lead pitch and 23.49mm package length. # multiplexed dram address inputs for reduced pin count and higher system densities. # selectable output operation (transparent / latched / registered) using set command register cycle. # single 3.3v +/- 0.3v power supply. (3.3v +/- 0.15v for -7 part) # 2048 refresh cycles every 64ms (ad0->ad10). # programmable burst length (1,2,4,8) and burst sequence (sequential,interleave) with no latency. # synchronous design for precise control with an external clock (k). # output retention by advanced mask clock (cms#). # all inputs/outputs low capacitance and lvttl compatible. # separate dram and sram address inputs for fast sram access. # page mode capability. # auto refresh capability. # self refresh capability. : master clock : chip select : dram clock mask : row addr. strobe : column addr. strobe : data transfer direction : dram address : sram clock mask : control clocks : write enable : i/o byte control : sram address : output enable : data i/o : power supply : dq power supply : ground :address fetch clock this pin can be none-connect. :must connect low :must connect high 1 description the m5m4v16169dtp/rt is a 16m-bit cached dram which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static ram array as a cache memory (block size 8x16) onto a single monolithic circuit. the block data transfer between the dram and the data transfer buffers (rb1/rb2/wb1/wb2) is performed in one instruction cycle, a fundamental advantage over a conventional dram/sram cache. the ram is fabricated with a high performance cmos process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low cost are essential. the use of quadruple-layer polysilicon process combined with silicide and double layer aluminum wiring technology, a single-transistor dynamic storage stacked capacitor cell, and a six-transistor static storage cache cell provide high circuit density at reduced costs. 22 28 30 32 14 7 19 20 21 23 24 25 26 27 29 31 33 34 35 1 2 3 4 5 6 8 9 10 11 12 13 15 16 17 49 43 41 39 57 64 52 51 50 48 47 46 45 44 42 40 38 37 36 70 69 68 67 66 65 63 62 61 60 59 58 56 55 54 vss dq9 as4 ad6 ad4 dq13 as9 dq11 vccq dq10 vss dq8 g# as5 as3 ad5 ad3 adf# vss vss ad9 ad8 ad7 ad10 as8 as7 as6 dq15 dq14 vccq dq12 vcc vss vss dq6 as2 cas# ad0 dq2 cs# dq4 vccq dq5 dq7 mch as0 as1 ras# dtd# ad1 ad2 vcc vcc dqcl dqcu cc1# cc0# we# cmd# cms# k dq0 dq1 vddq dq3 vss package code:70p3s-l 400 mil 70pin tsop type ii 0.65mm lead pitch ad11 mcl features power dissipation (typ) sram access/cycle dram access/cycle 8.0ns/15ns 75ns/120ns type name 56ns/80ns m5m4v16169tp/rt-15 6.4ns/8ns dram: 500 sram: 800 dram: 330 sram: 420 m5m4v16169tp/rt-8 m5m4v16169tp/rt-7 5.6ns/7ns 49ns/70ns dram: 530 sram: 860 22 28 30 32 14 7 19 20 21 23 24 25 26 27 29 31 33 34 35 1 2 3 4 5 6 8 9 10 11 12 13 15 16 17 vss vss dq6 as2 cas# ad0 dq2 cs# dq4 vccq dq5 dq7 mch as0 as1 ras# dtd# ad1 ad2 vcc vcc dqcl dqcu cc1# cc0# we# cmd# cms# k dq0 dq1 vccq dq3 vss package code:70p3s-m 400 mil 70pin tsop type ii 0.65mm lead pitch vss dq9 as4 ad6 ad4 dq13 as9 dq11 vccq dq10 vss dq8 g# as5 as3 ad5 ad3 adf# vss vss ad9 ad8 ad7 ad10 as8 as7 as6 dq15 dq14 vccq dq12 vcc ad11 49 43 41 39 57 64 52 51 50 48 47 46 45 44 42 40 38 37 36 70 69 68 67 66 65 63 62 61 60 59 58 56 55 54 mcl pinconfiguration (top view) k cs# cmd# ras# cas# dtd# ad cms# cc0#,cc1# we# dqc(u/l) as g# dq vcc vccq vss adf# mcl mch 60ns/90ns 8.0ns/10ns dram: 430 sram: 660 m5m4v16169tp/rt-10
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric block diagram 1 1m bit dram array column block decoder sense amplifier and i/o control kbuffer timing control main amp. din buffer col.3-7 row 0-11 command (0-6) 0 1 2 7 as3-9 as0-2 dqcu (enable upper) mask mask vcc vss 0 2 1 (row address strobe) (column address strobe) (data transfer direction) (clock mask for dram) (master clock) (clock mask for sram) (write enable) (control clock 0) (control clock 1) 7 0 7 1 16 1m x 16= 16m dram dqcl (enable lower) 2 s/a and i/o 1kbit sram array write buffer 2 write buffer 1 read buffer1 1kx16=16k sram col.decoder wb2 mask wb1 mask (chip select) read buffer2 rb1 rb2 wb2 wb1 wb2m wb1m ad11 66 ad10 65 ad9 69 ad8 68 ad7 67 ad2 34 ad1 33 ad0 32 vccq 1 54 35 12 23 48 59 70 17 36 15 20 51 56 ras# 29 cas# 30 dtd# 31 cmd# 8 cs# 7 k 10 cms# 9 we# 6 cc0# 5 cc1# 4 3 2 dq0 11 dq1 13 dq2 14 dq3 16 dq4 19 dq5 21 dq6 22 dq7 24 dq8 47 dq9 49 dq10 50 dq11 52 dq12 55 dq13 57 dq14 58 dq15 60 as9 64 as8 63 as7 62 as6 61 as5 44 as4 43 as3 42 as2 28 as1 27 as0 26 45 g# (address fetch) adf# 37 ad6 41 ad5 40 ad4 39 ad3 38 dram address input sram address input (output enable)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 3 8x16 ad0-11 1 of 4096 decode ad3-7 1 of 32 decode 8x16 block rb2 dqs 8x16 8x16 8x16 16 bits 16 bits 16 bits 16 bits 8x16 block upper byte lower byte upper byte lower byte upper byte lower byte rb1 upper byte lower byte 8x16 wb2 as0-2 1of8decode block diagram 2 as3 - 9 1 of 128 decode as0-2 1of8decode dram row decoder wb1 as0-2 1of8 decode sram 1kx16 sram row decoder dram 1mx16 dq0-7 dq8-15
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric function truth table h h x x x x x x x nop h cs# cms# cas# dqc (u/l) we# cc0# cc1# mnemonic code previous ras# dtd# ad2 dram ad ( dram address ) ad1 ad0-11 as sram (sram address) as0-9 previous cmd# ad0 x x 4 x x x x x x x x x x spd l x x l x x x x x x x h h des h x sr l x x x x as0-9 h h h l h x l x x x x as0-2 h h l l br h x l x x x x as0-2 h l l l bw h x l x x x x as0-9 h l h l sw h x l x x x x as3-9 l h l h brt h x bwt l x x x x as3-9 l l l h h x l x x x x as0-9 h h l h brtr h x bwtw l x x x x as0-9 h l l h h x dpd x x x x x x x x x x l l h h x x x x x x x dnop x h drt l h l h ad3-7 (col.block) x x x x x x h 0 0 0 l h l l 0 0 ad3-7 (col.block) x x x x x dwt1 x h 0 l 0 0 h l l ad3-7 (col.block) x x x x x dwt1r x h 1 l 0 1 ad3-7 (col.block) h l l x x x x x dwt2 x h 0 l 0 1 ad3-7 (col.block) h l l x x x x x dwt2r x h 1 (2) (2) (2) (2) (1) (1) (1) (2) (2) (2) (2) (2) l l l h x x x x x x arf x h l l l l command x x x x x scr x h l l h l x x x x x x pcg x h l l h h ad0-11 (row add.) x x x x x act x h l l l h x x x x x x srf x h (7) (8) notes 1) for the dpd function, the ras#, cas# and dtd# inputs are don't care except for the l,l,h combination. (respectively). 2) the unused addresses must be set to low. 3) use new: if bw or bwt or bwtw is initiated the same cycle as dwt1 or dwt1r, new data is loaded into the buffer and transferred to dram. 4) clear 1 or 2 transfer mask bits (as addressed by as0-2 and dqcu/l). 5) actual number of bits transfer depends on the state of the dtbw mask and the dqcu/dqcl inputs. note: if dqc(u/l) is low, the corresponding dq(s) is(are) disabled (input and output buffer). sr,sw,br and bw cycles with dqcu and dqcl low result in a deselect sram operation. 6) following a dwt1 or dwt1r cycle, the entire wb1 transfer mask is set . (i.e. , data can no longer be transferred from wb1 to dram.) succeeding buffer-writes or buffer write transfers will clear mask bits. 7) cmd# during current cycle must be high (see timing diagram for auto-refresh). 8) cmd# during current cycle must be low (see timing diagram for self-refresh). l x x x x h l h h x lbm h x l h l l 1 0 ad3-7 (col.block) x x x x x dwt3 x h 0 l 1 0 h l l ad3-7 (col.block) x x x x x dwt3r x h 1 l 1 1 ad3-7 (col.block) h l l x x x x x dwt4 x h 0 l 1 1 ad3-7 (col.block) h l l x x x x x dwt4r x h 1 (2) (2) (2) (2)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 5 function truth table do: data out din: data in wb1: write buffer 1 wb2: write buffer 2 rb: read buffer function din --> sram din --> wb1 sram --> wb1 wb1 --> wb2 wb2 --> dram data transferred (max) 8/16 bits 8/16bits 128 bits (8x16bit-block) 128 bits (8x16bit-block) 128 bits (8x16bit-block) (5) (5) function wb2 --> rb dram --> rb rb --> dout rb --> sram data transferred (max) 128 bits (8x16bit-block) 128 bits (8x16bit-block) 8/16 bits 128 bits (8x16bit-block) (5) data transfer buffers xfer masks clear mask write buffers wb1 read buffer rb1,2 din dout function dq pin no operation hi-z deselect sram sram read sram->do sram write din->sram buffer read xfer use hi-z rb2->sram dram power down buffer read valid use rb2->do buffer write valid hi-z din->wb1 buffer read xfer & read valid use rb2->sram->do auto refresh set command register buffer write xfer sram->wb1 valid hi-z din->sram->wb1 dram no operation dram activate dram precharge dram read xfer load dram->rb1->rb2 dram write xfer1 wb1->wb2->dram load dram write xfer1& read wb1->wb2 ->dram->rb1->rb2 dram write xfer2 wb2->dram load dram write xfer2& read wb2->dram ->rb1->rb2 self refresh entry page call clear 1 or 2 bits use wb2 clear mask wb1 mask wb2 mask use load/ use use use load/ use load/ use load/ use use use use use load load load - - - - - (6) (6) (4) (3) (3) no operation no operation sram power down& suspend no operation data retention - hi-z no operation buffer read xfer & read valid hi-z valid hi-z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - hi-z - - - - byte mask - dram power down no operation dram write xfer3 wb1->wb2->dram load dram write xfer3& read wb1->wb2 ->dram->rb1->rb2 dram write xfer4 wb2->dram load dram write xfer4& read wb2->dram->rb use use load/ use load/ use - - use use (3) - - - - - - - - - - - - - - load - - load
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 6 master clock provides the fundamental timing and the internal clock frequency for the cdram. all external timing parameters (with the exception of g# in read cycle and cmd# in self refresh cycle) are specified with respect to the rising edge of k. dram clock mask controls the operation of the internal dram master clock (k). when cmd# is low at the rising edge of k, the internal dram master clock (k) for the following cycle is ceased and input stages are powered-off, resulting in a dram power down. row address strobe is used in conjunction with master clock k (depending on the states of cmd#, cas#, and dtd#) to activate the dram (latching the row address lines and accessing 1 of 4096 rows), initiate a dram precharge cycle, perform a dram read or write transfer, dram write transfer & read, set the command registers, start an auto-refresh cycle, enter a self-refresh cycle,create a dram nop cycle, or power down the dram. column address strobe is used in conjunction with the master clock k to latch the column addresses. when preceded by ras# in a dram access cycle, cas# initiates a dram write transfer (wb1/2 -> dram, if dtd#=l), dram write transfer & read (wb1/2 -> dram -> rb, if dtd#=l) or dram read transfer (dram -> rb, if dtd#=h), depending on the state of dtd# (see dtd# pin description). data transfer direction controls dram-to-rb(read) / wb-to-dram (write) direction. if preceded by a ras# low cycle, both cas# and dtd# low (on the rising edge of k) initiate a dram write transfer cycle. if dtd# stays high with the above conditions, a dram read transfer cycle results. dtd# can also initiate dram activate, dram precharge, auto-refresh, set-command register, and self refresh cycles. dram address lines are multiplexed to reduce pin count. ad0-ad11 (@ ras=low,cas=high,dtd=high, k=rising edge) specify the row address of the dram to activate and refresh the selected page and ad3-ad7 (@ ras=high,cas=low,k=rising edge) specify the block address of the dram. in addition, ad0-ad2 (@ ras=high,cas=low, k=rising edge) specify the transfer operation of the dram . also ad0-ad9 (@ras=low,cas=low, dtd=low, k=rising edge) are used as the command in set command register cycle. the chip select controls the operation of the cdram. when cs#=h at the rising edge of k and the previous cmd# or cms# is high, the chip is in no operation mode. sram clock mask controls the operation of the internal sram master clock (ks). when cms# is asserted at a rising edge of k, the internal sram master clock for the following cycle is suspended, resulting in the power down of the sram portion of the circuit, including the sense amps. cms# can also be used to retain output data during sram power-down. input input input input input input input input k cmd# ras# cas# dtd# ad0-ad11 cs# cms# pin descriptions(1)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 7 dqcu/l are i/obyte control signals. if g#=low, dqcu/l have a control of output impedence: dqcu controls upper dqs (dq8-15) & dqcl controls lower dqs (dq0-7). dqcu/l also control both input data during sram writes or buffer writes and transfer mask during buffer writes. (wb1 transfer masks for each byte are written (bits are cleared) during buffer writes depending on dqcu/l inputs.) input dqcl,dqcu we# cc0#,cc1# as0-as9 g# dq0-dq15 vccq input inputs inputs input inputs / outputs supply write enable controls sram and buffer read and write operations. a high on the we# pin causes either a buffer read, sram read, buffer read transfer and/or a buffer read transfer & read to occur (depending on the state of the cc0# and cc1# bits). a low on the we# pin causes either a buffer write, sram write, buffer write transfer and/or a buffer write transfer & write to occur (depending on the state of the cc0# and cc1# inputs) the control clock inputs control sram and buffer operations. cc0# is low for all buffer writes, reads, and transfers, and high for all other sram operations. cc1# is high for all buffer read transfers and buffer write transfers , and deselect sram. sram addresses are non-multiplexed, and access 1024 - 16-bit words ( configured as 128 rows x 8 columns x 16 bits, where the block size is 8 x 16) in the sram array. as0-as3 select word address within a block, and as3-as9 select the sram row(block). the output enable is an asynchronous input. g#=high forces the outputs to high impedence. output operation is either transparent, latched , or registered depending on the state of the command register. the data lines for the cdram are asynchronously controlled by g#. vccq is the dq power supply and allows the device to operate in a mixed voltage system (e.g., 5v data bus). as specified in the table: recommended operating conditions, vccq must be greater-than or equal-to the highest voltage experienced by the data bus. for 3.3v system operation, vccq may be tied to vcc. pin descriptions(2)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 8 nop sram power-down deselect sram sram read sram write no operation. outputs are high-impedance. all input buffers remain active. if cms#=low at the rising edge of k, the sram enters sram power down at the next rising edge of k. during this mode, the internal sram k clock becomes inactive. the output buffers remain enabled and are controlled by g#. all input buffers of sram clocks and sram addresses are inactive. all transfer functions and input/output operations to and from the sram and buffer are disabled. this cycle is useful for output impedance control (hi-z,low-z) without g#. output buffers are active during this cycle for registered output mode control. data is read from the sram to the i/o pins. addresses as0-as9 are used to select the data to be read. as3-as9 decode the sram row (=block), and as0-as2 decode (1 of 8) the 16- bit word. dqcu and dqcl control the impedence (high-z/low-z) of the upper and lower bytes, respectively. data is written from the i/o pins to the sram. addresses as0-as9 are used to select the location to be written. as3-as9 decode the sram row (=block), and as0-as2 decode (1of8) the 16-bit word to be written. dqcuu and dqcl control upper and lower byte writes, respectively. x dqs sram 1kx16 8x16 8x16 8x16 8x16 16bits 16bits as3-9 1of128decode ad0-9 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte wb2 rb1 mode descriptions (1) dram 1mx16 16bits sram rowdecoder 8x16 upper byte lower byte upper byte lower byte dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric buffer read transfer buffer write transfer data is transferred from the read buffer (rb2) to the sram. addresses as3-9 select the sram row to which the 8x16 bit block is to be written. addresses as0-as2 must be set low. data is transferred from the sram to the write-buffer1 (wb1). addresses as3-as9 decode the sram row (=8x16 bit block) to be transferred. addresses as0-as2 must be set low. the buffer write transfer cycle "clears" all transfer mask bits in the wb1 mask (allowing all data to be transferred in a successive dram write transfer cycle). mode descriptions (2) 9 x dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte upper byte lower byte rb1 ad0-11 x dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric buffer read transfer & sram read buffer write transfer & sram write data is transferred from the read buffer (rb2) to the sram, and simultaneously, data (16 bit word) is read from the rb2 to the i/o pins. addresses as3-9 select the sram row to which the 8x16 bit block is to be written. addresses as0-as2 decode the 16-bit word to be read. data is first written from the i/o pins to sram as decoded by as0-as9. then, the sram row (=block) decoded by as3-as9 is transferred to the write-buffer1 (wb1). the buffer write transfer cycle "clears" all transfer mask bits in the wb1 mask (allowing all data to be transferred in a successive dram write transfer cycle). dqcu and dqcl control upper and lower byte writes respectively, however all transfer mask bits in the wb1 are cleared. mode descriptions (3) 10 x dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte upper byte lower byte x dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 rb1 rb2 wb2 upper byte lower byte wb1 dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric buffer read buffer write data is written from the i/o pins to the write-buffer1. addresses as0-a2 are used to select (1of8) the 16-bit word to be written. addresses as3-as9 must be set low for this operation. the transfer mask bits associated with the upper and lower bytes are cleared in the wb1 mask. dqcu and dqcl control upper and lower byte writes (and associated tranfer mask bits), respectively. data is read from the read buffer (rb2) to the i/o pins. addresses as0-as2 are used to select (1 of 8) the 16-bit word to be read. addresses as3-as9 must be set low for this operation. mode descriptions (4) 11 dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 wb2 upper byte lower byte x rb1 x dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric mode descriptions (5) 12 dram read transfer a block (8x16) is transferred from the dram to the read buffer1 and 2 (rb1,rb2) as specified by addresses ad3-ad7. addresses ad8-ad11 and ad0-ad2 must be set to low. after the latency period (specified in the access latency table) new data will be present in the read buffer2. prior to the latency timeout, old data will be present in the rb2. (notes 1,2,4) dram power-down dram nop if cmd#=low at the rising edge of k, the dram enters dram power down at the next rising edge of k. during this mode, the internal dram k clock becomes inactive. also all input buffers of dram clocks and dram addresses are inactive. note that the latency of dram read transfer cycle is not counted up in this cycle. the dnop cycle is used when no other dram operations are desired, holding the dram in its present (precharge/activate) state. dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 x wb2 upper byte lower byte dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric dram write transfer1 data (8x16 block) is transferred from wb1 through wb2 to the dram block specified by addresses ad3-ad7. addresses ad8-ad11 must be set to low. the mask present in wb1 is also transferred to wb2 and controls the data written to the dram. after data has been transferred from wb1 to wb2 in the present cycle, the entire wb1 mask is set. (notes 3,4) dram write transfer1 & read data (8x16 block) is transferred from wb1 through wb2 to the dram block specified by addresses ad3-ad7. addresses ad8-a11 must be set to low. the transfer mask present in wb1 is also transferred to wb2 and controls the data written to the dram. the block to which the data is written in dram is simultaneously transferred to the read buffer.(notes 2,3,4) 13 x sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 1m x 16 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte upper byte lower byte rb1 ad0-11 x dqs mode descriptions (6) wb2 dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric dram write transfer2 dram write transfer2 & read data (8x16 block) is transferred from wb2 to the dram block specified by addresses ad3- ad7. addresses ad8-ad11 must be set to low. the wb2 mask controls the data written to the dram. with the dwt2 function, the wb2 data and wb2 transfer mask remain unchanged. (note 4) data (8x16 block) is transferred from wb2 to the dram block specified by addresses ad3- ad7. addresses ad8-ad11 must be set to low. the wb2 transfer mask controls the data written to the dram. with the dwt2 function, the wb2 data and wb2 transfer mask remain unchanged. the block to which the data is written in dram is simultaneously transferred to the read buffer1 and 2. (notes 1,2,4) mode descriptions (7) 14 dqs 8x16 8x16 8x16 8x16 8x16 16bits 16bits as3-9 1of128decode 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte upper byte lower byte rb1 ad0-11 x dqs 8x16 8x16 8x16 8x16 16bits 16bits as3-9 1of128decode 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte upper byte lower byte rb1 ad0-11 x wb2 sram rowdecoder dram 1m x 16 sram 1kx16 16bits sram 1kx16 dram 1mx16 8x16 16bits sram rowdecoder dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric dram write transfer3 data (8x16 block) is transferred from wb1 through wb2 to the dram block specified by addresses ad3-ad7. addresses ad8-ad9 must be set to low. the mask present in byte maskregister controls the data written to the dram. the byte mask register is set at load byte mask cycle,where corresponding byte masks are set depending on dq data in the cycle. (note 4,5) the data of wb1 and the mask data of wbm1 are tranferred to wb2 and wbm2, however wbm1/2 is not used in this cycle. dram write transfer3 & read data (8x16 block) is transferred from wb1 through wb2 to the dram block specified by addresses ad3-ad7. addresses ad8-ad9 must be set to low. the mask present in byte maskregister controls the data written to the dram. the block to which the data is written in dram is simultaneously transferred to the read buffer.(notes 1,2,4,5) mode descriptions (8) 15 x dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 256kx16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 x dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 256kx16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric dram write transfer4 dram write transfer4 & read data (8x16 block) is transferred from wb2 to the dram block specified by addresses ad3- ad7. addresses ad8-ad9 must be set to low. the mask present in byte maskregister controls the data written to the dram. with the dwt4 function, the wb2 data and wb2 mask remain unchanged. (note 4,5) data (8x16 block) is transferred from wb2 to the dram block specified by addresses ad3- ad7. addresses ad8-ad9 must be set to low. the mask present in byte maskregister controls the data written to the dram. with the dwt4r function, the wb2 data and wb2 transfer mask remain unchanged. the block to which the data is written in dram is simultaneously transferred to the read buffer. (notes 1,2,4,5) mode descriptions (9) 16 x dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits 16bits as3-9 1of128decode sram rowdecoder dram 256kx16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block wb1 upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 dqs sram 1kx16 8x16 8x16 8x16 8x16 8x16 16bits 16bits as3-9 1of128decode sram rowdecoder dram 256kx16 ad0-11 1of4096decode ad3-7 1of32 decode as0-2 1of8 decode as0-2 1of8decode 8x16block 8x16block upper byte lower byte wb2 upper byte lower byte dram rowdecoder 16bits as0-2 1of8decode upper byte lower byte rb2 upper byte lower byte rb1 wb1 x 16bits dq8-15 dq0-7 dq8-15 dq0-7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric mode descriptions (10) notes: 1) this function is performed in a latency period specified in the access latency table. 2) after the latency period (specified in the access latency table) new data will be present in the read buffer2. prior to the latency timeout, old data will be present in the rb2. 3) after data has been transferred from wb1, the entire wb1 mask is set. 4) valid ad0-ad2 addresses are shown in the function truth table. dram activate dram precharge dram auto-refresh dram self refresh addresses are latched from the ad0-ad11 inputs by the rising edge of k. internally, a dram row is selected (page call) in preparation for a dram read or write transfer cycle. a dram precharge cycle must separate all dram activate cycles. internally, the active dram row is deselected (completing the refresh process) and page-mode is disabled. the dram is precharged prior to another dram activate cycle. internally, a dram row is selected and refreshed (as addressed by an internal, self-incrementing counter), followed by an internally generated precharge cycle. the auto refresh cycle can be implemented only if the dram is in precharge state (i.e., a precharge or auto-refresh cycle occurred more recently than an acitvate cycle). dram auto-refresh is similar to a cas-before- ras (cbr) mode in standard drams. all clock buffers are suspended, and cmd# asynchronously controls self refresh (cmd# rising edge initiates exit from self refresh). during self refresh, device enters a low power mode, with 2048 automatic refresh cycles. set command register when scr is initiated,the addresses present on the ad0-ad11 dram address pins determine the dram read transfer latency, the output mode (transparent / latched / registered), and wb1 transfer mask mode (set-all/ no change). no dram operation is executed in this cycle. refer to the scr truth table for legal address values. during scr cycle and the following 3 clock cycles(totally 4 clock cycles), only nop,dnop ordpd are allowed in dram portion and only nop,des or spd are done in sram portion. the set commands are valid at least after the above 4 clocks later and the previous function is not guaranteed to work if it has not been completed.(i.e. drt ,dwt1&r,dwt2&r and sr,br and brtr with registered output mode.) 17 power-on sequence before starting normal operation, the following power on sequence is necessary. 1) apply power and maintain stable power (pause) for 500us. 2) perform a precharge (pcg) operation. 3) after trp, perform 8 auto refresh commands (arf) with adequate interval (trc). 4) issue set command register (scr) to initilize the mode register. after this sequence, the ram is in idle state and ready for normal operation. note that dnop / dpd and des / spd or nop command will be the stand-by command for the above power sequence. vcc must be powered-on at the same time or before vccq is on. and vcc must be powered-off at the same time or after vccq is off.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric output operations transparent k dqc g# dq0-15 tkla tklqx tklqz q latched q tghq k dqc g# dq0-15 tkha tglq tgla sr sr des sr sr des tkla tkha output appears from the rising edge of k clock. k dqc g# dq0-15 tkha tkhqx tkhqz q tglq q tghq k dqc g# dq0-15 tgla sr sr sr sr des des tkha output appears from the falling edge of k clock. registered k dqc g# dq0-15 tkhqx tkhqz q tglq q tghq k dqc g# dq0-15 tkhar tkhqz tgla sr sr sr des des sr sr sr tk tkhar tk output appears from the rising edge of k clock. 18 this outputmode was deleted.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k,k# t k t kh t kl cmd# t cmds t cmdh ras# cas# cms# dtd# t rs t rh t cs t ch t cmss t cmsh t dts td th dq0-15 (input) ad0-11 as0-9 t ds t dh t as t ah dqc(u / l) t dqcs t dqch we# t ws t wh cc0# cc1# t c0s t c0h t c1s t c1h cs# t css t csh 19 ts th adf# t sadf t hadf
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric load byte mask byte mask allocation during dwt3 and dwt4 column block (16 byte) upper lower 0 byte mask register dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lower dqs upper dqs 0 : mask, no write 1 : unmask, write enable 20 block address 1 2 3 4 5 6 7
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric as0-2 dqcl dqcu wm1 sram dram dq0-15 wb1 wb2 wm2 dwt3/dwt4 dwt1 dwt2 dwt1/dwt3 dwt2/dwt4 addition load byte mask (lbm) 0 1 2 3 4 5 6 7 128 set 0 --- 1023 dram row 0 255 dram column wb1/wb2 dwt3 / dwt4 upper8 bit lower 8bit byte mask sram 0 1 0 1 1 1 0 0 written byte mask 0 1 0 1 1 0 1 0 0 byte mask bit write data / mask data write / mask logic 21 lower byte upper byte dq0-> ->dq15 1 1 1 1 0 0 1
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric dwt3-dwt4 for window clear(block write) window boundary page boundary shadow clear / window clear bwt des lbm dwt3 dwt4 dwt4 act dnop dnop dnop dnop des lbm des des des dwt4 dnop des des dwt4 lbm pcg des color data is loaded from sram cache to wb1.(bwt) page call.(act) color data is transferred from wb1 through wb2 to dram column block with byte mask, which is loaded by load byte mask cycle(lbm). the byte mask data is valid from the lbm cycle immediately and lasts until the next lbm cycle is initiated. color data is transferred from wb2 to dram column block with byte mask. color data is transferred from wb2 to dram column block with new byte mask. 22
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric burst mode (1) sram address and dram address can be multiplexed using this duration for dram control k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 as0-2 g# dq0-15 as3-11 l q1+1 q1+3 dqc(u / l) we# cc0# cc1# adf# des sr sr sr sr des sr sr sr sr sr sr sr q1 q1+2 q2 c1 c2 c3 c1 c2 c3 q3 q3+2 q2+1 q3+1 q3+3 q3 accept interrupt for inputting new address w/o gap. 23 cms#
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 as0-2 g# dq0-15 as3-11 l q1+1 d2 dqc(u / l) we# cc0# cc1# adf# des sr des sr spd spd des sw sw sr sr sr sr q1 d1+2 c1 c2 c3 q4 q3 q5 q6 c4 c5 c6 c1 c2 c3 c4 c5 c6 burst address is not incremented by des, spd. adf#=low is equal to non-burst mode. "insert wait" is possible. burst mode (2) m5m4v16169d keeps compatibility setting adf# low or setting burst length=1 by scr cycle. (ad7, ad8 and ad9=0) 24 cms#
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 1000 symbol parameter conditions ratings unit vcc supply voltage with respect to vss -0.5 ~ 4.6 v v i input voltage -0.5 ~ 4.6 v v o output voltage -0.5 ~ 4.6 v i o output current 50 ma pd power dissipation mw topr operating temperature 0 ~ 70 ? tstg storage temperature -65 ~ 150 recommended operating conditions symbol parameter limits unit min. typ. max vcc supply voltage 3.0 3.3 3.6 v vss supply voltage 0 0 0 v v capacitance symbol parameter test condition limits (max) unit c i(a) input capacitance, address pin v i =vss 5 pf c i(c) input capacitance, clock pin f=1mhz 5 pf c i/o input capacitance, i/o pin v i =25mvrms 7 pf ? vccq supply voltage for output 3.0 3.3 3.6 25 (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted) v il v ih (lvttl) (lvttl) low-level input voltage all inputs high-level input voltage clock and add. 2.0 vdd+0.3 -0.3 0.8 v v (lvttl) high-level input voltage data pin 2.0 vddq+0.3 v v ih absolute maximum ratings **-15 spec is the same as m5m4v16169tp/rt-15 (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted) (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted) v ih (lvttl) high-level input voltage master clock (k) 2.2 vdd+0.3 v
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric average supply current from vcc symbol condition limits (max) output open iccs average supply current of sram operating, tk=min. dram=dpd iccd average supply current of dram operating, trc=min. sram=spd icc(stn1) lvttl standby, tk=min, dram=dnop&sram=des, or nop all input=stable. icc(stn2) cmos standby, tk=min, dram=dnop&sram+des, or nop all input=stable. icc(pd) cmos power down current, cmd#=cms#=l,tk=min. * voh(ac) and vol(ac) are the reference levels for ac measurements. voh(dc) and vol(dc) are the final levels the outputs reach. ac operating conditions and characteristics symbol parameter test condition limits unit min. max v v i oz off-state output current q floating v o =0 ~ vddq -10 10 ua i i input current v ih =0 ~ vddq+0.3v -10 10 ua -8 -10 5 icc(srf) cmos self refresh current, cmd#=cms#=l,tk= 1 1 5 iccd(pg) average supply current of dram page-mode tpc=min. sram=spd output open output open data input=h or l data input=h or l data input=h or l -7 5 1 vtt 50ohm 30pf v out ac condition (access time) 260 240 200 160 150 130 140 130 110 60 60 50 50 50 40 26 voh(dc)* (lvttl) vol(dc)* (lvttl) high-level output voltage (dc) low-level output voltage (dc) ioh= -2ma iol= 2ma 2.4 0.4 - - **-15 spec is the same as m5m4v16169tp/rt-15 unit ma ma ma ma ma ma ma -15 1 5 140 100 80 30 25 (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted) (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric timing requirements (clk pulse, input signals setup / hold time to clk edge) input pulse levels: input timing measurement reference level: symbol parameter min. max tk clock cycle time tkh clock high pulse width tkl clock low pulse width ts setup time for inputs th hold time for inputs 8 3 3 3 1 limits min. max 10 -8 -10 unit ns ns ns ns ns 3.5 4 3 1 -7 min. max 7 3 3 3 1 27 **-15 spec is the same as m5m4v16169tp/rt-15 vih=3.0v,vil=0.0v (lvttl) 1.5v (lvttl) min. max -15 15 5 5 4 1 (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric timing requirements (read, write, refresh) symbol parameter unit min. max tref refresh cycle time ms trp precharge time ns trcd delay time, add strb. row to col. ns ns trc* dram activate-read cycle time twc* dram activate-write cycle time ns tpc page cycle time ns tras activate time ns trwl write to precharge lead time ns trsh read to precharge hold time ns 64 24 24 80 56 16 16 16 80 limits min. max 64 -8 -10 10,000 30 30 90 60 20 20 20 90 10,000 trasp page mode activate time ns 56 100,000 60 100,000 *note: when trp and tras = min. values, trc and twc = trp + tras. min. max -7 64 21 21 70 49 14 14 14 70 10,000 49 100,000 28 **-15 spec is the same as m5m4v16169tp/rt-15 input pulse levels: input timing measurement reference level: vih=3.0v,vil=0.0v (lvttl) 1.5v (lvttl) -15 min. 40 30 120 70 20 20 30 120 70 12,000 100,000 max 64 (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric switching characteristics symbol parameter unit min. max tcbf buffer-fill from dram read transfer ns limits min. max -8 -10 20 20 tkha access time from k-high edge tkhqx output active time from k-high edge ns tkhqz output disable time from k-high edge ns ns ns ns 10 access time from k-high edge output active time from g#-low edge output disable time from g#-high edge tkhar tglq tghq 2 6.4 7 6.4 8 ns ns ns tkhqxr output active time from k-high edge tkhqzr output disable time from k-high edge 2 2 tgla access time from g#-low edge 6.4 7 0 0 ns min. max -7 20 5.6 5.6 2 5.6 0 2 2 2 2 8 10 7 2 2 2 10 29 **-15 spec is the same as m5m4v16169tp/rt-15 min. max 20 15 3 12 3 3 3 5 -15 (ta=0~70? , vdd=3.3?.3v for -8,and -10, vdd=3.3?.15v for -7 vss=0v, unless otherwise noted)
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric ( sram read/deselect sram/sram write/sram power-down ) 30 non-g# controlled write & read (des control) note : output is transparent. k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 as0-2 g# dq0-15 as3-9 l q2 q4 dqc(u / l) we# cc0# cc1# cms# cs# des sw sr des sw sr des sw sr spd spd spd des d1 d3 d5 q6 c1 c2 c3 c4 c5 c6 c1 c2 c3 c4 c5 c6 dram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric note : output is transparent. 31 ( sram read/deselect sram/sram write/sram power-down ) g# controlled write & read k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cms# as0-2 g# dq0-15 as3-9 h cc0# cc1# cs# l dqc(u / l) we# des sw sr spd spd spd des sr sw sr sr sr des d1 c1 c1 c2 c2 q2 c3 c3 c4 c4 q3 d4 q5 q6 q7 c5 c5 c6 c6 c7 c7 dram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 32 ( sram read/deselect sram/sram write/sram power-down ) dqc controlled write & read k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 as0-2 g# dq8-15 as3-9 l dqcu we# cc0# cc1# cms# cs# des sw sr des sw sr des sw sr spd spd spd des q6 c1 c2 c3 c4 c5 c6 c1 c2 c3 c4 c5 c6 dqcl dq0-7 (u/l) (u/l) (l) (l) (u) (u) q2 d1 d3 q4 h or l note : output is transparent. dram operation can be freely performed. d1 q2 d5
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 33 registered output control k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 as0-2 g# dq0-15 as3-9 l dqc(u / l) we# cc0# cc1# cms# cs# des sw sr sr sw sr sr sw spd spd des c1 c2 c4 c5 c7 c8 sw des d1 q8 q2 d3 q4 d5 q6 d7 c3 c6 note : output is registered. ( sram read/deselect sram/sram write/sram power-down ) dram operation can be freely performed. c1 c2 c4 c5 c7 c8 c3 c6
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 34 k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cms# as0-2 g# dq0-15 as3-9 h cc0# cc1# cs# l dqc(u / l) we# des brt sr sr sr sr brtr sr sr sr des des des (c1) (c1) c1 (c1) c2 (c1) c3 q5 q6 q7 (c1) c4 (c5) c5 (c5) c6 des q1 q2 q3 q4 q8 (c5) c7 (c5) c8 l buffer read transfer (rb2 -> sram) buffer read transfer & sram read (rb2 -> sram -> output) note : output is transparent. dram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric buffer write transfer (sram -> wb1) 35 k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cms# as0-2 g# dq0-15 as3-9 h cc0# cc1# cs# l dqc(u / l) we# des des bwt des des bwtw des des bwt des des des des c1 c2 c2 des d2 c3 l wb1(0-7) d1 d2 d3 old buffer write transfer & sram write (input -> sram -> wb1) note : output is transparent. dram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric buffer read (rb2 -> output) 36 buffer write (input -> wb1) note : output is transparent. k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cms# as0-2 g# dq0-15 as3-9 h cc0# cc1# cs# l dqc(u / l) we# bw bw bw bw des des des des br br br br des c3 c4 c5 q5 q6 q7 c6 c7 c8 des d1 d2 d3 d4 q8 l wb1(0-7) d1 d2 d3 d4 c2 c1 wb1 mask(0-7) d1 d2 d3 d4 dram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric no - operation of sram k cs# 2 3 4 5 6 7 8 9 10 11 12 13 14 1 no-operation mode cms# cc0# cc1# we# dqc(u / l) as0-9 h nop nop nop nop nop nop nop nop nop nop nop nop cas# dtd# ad0-11 ras# cmd# dram operation can be freely performed. 37
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric no - operation of dram 38 k cs# 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cas# dtd# ad0-11 no-operation mode ras# h cmd# nop nop nop nop nop nop nop nop nop nop nop nop cms# dqc(u/l) we# cc0# cc1# g# as0-9 dq0-15 sram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 39 k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cmd# ras# cas# dtd# ad0-11 cs# dpd dpd dpd act dnop dnop dnop dnop pcg dpd dpd dpd dpd row dpd is recommended during no operation to save power. dram power down / dram activate / dram precharge cms# dqc(u/l) we# cc0# cc1# g# as0-9 dq0-15 sram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 40 dram power down / dram activate / dram precharge ras only refresh cycle k 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cmd# ras# cas# dtd# ad0-11 cs# pcg dpd dpd act dnop dnop dnop dnop pcg dpd dpd dpd dpd row trc trp tras cms# dqc(u/l) we# cc0# cc1# g# as0-9 dq0-15 sram operation can be freely performed.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k dram auto refresh 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-11 cmd# cms# dqc(u/l) we# cc0# cc1# g# as0-9 dq0-15 sram operation can be freely performed. cs# note: dram must be in precharge state prior to auto-refresh cycle. dpd dpd arf dnop dpd dpd dpd dpd dpd dpd arf dnop trc dnop dnop dram new commands except for nop,dnop and dpd can be set after trc later from arf command input. h h h h 41
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric dram self refresh self refresh entry: (note: dram must be in precharge state prior to self-refresh entry) previous cmd#=h, present cmd#=l, cs#=ras#=cas#=l, dtd#=h (cmd# must remain low to maintain self refresh). self refresh exit (in order): a) resume k clock b) cmd#=h c) wait trc for recovery d) resume normal operation k 2 3 4 1 ras# cas# dtd# ad0-11 cmd# self refresh entry self refresh mode trc for recovery cs# self refresh sram power down exit h l 1 2 3 4 5 6 l inhibit falling edge. l l row dnop dnop srf halt halt halt dnop dnop dnop dnop act dnop h h 42 sram power down mode
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 43 k cmd# dram read transfer (dram -> rb1-> rb2) latency set= 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 rb1 new data old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act drt pcg dpd dnop dnop dpd dpd dpd br br br br br br br br br br br br br br dq0-15 trc trp trcd row row tcbf tras trsh old old old old old old old old old new new new new new dram sram new data old data rb2 latency x t k
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# dram read transfer (dram -> rb1-> rb2) latency set= 2 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-9 rb1 new data old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act drt pcg dpd dnop dnop dpd dpd dpd br br br br br br br br br br br br br br dq0-15 trc trp trcd row row tcbf tras trsh old old old old old old old old old new new new new dram sram old 44 rb2 new data old data latency x t k
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# dram read transfer (dram -> rb1-> rb2) latency set= 3 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 rb1 new data old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act drt pcg dpd dnop dnop dpd dpd dpd br br br br br br br br br br br br br br dq0-15 trc trp trcd row row tcbf tras trsh old old old old old old old old old new new new dram sram old old 45 rb2 new data old data latency x t k
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# dram read transfer (dram -> rb1-> rb2) latency set= 4 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 rb1 new data old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act drt pcg dpd dnop dnop dpd dpd br br br br br br br br br br br br br br dq0-15 trc trp trcd row row tcbf tras trsh old old old old old old old old old new new dram sram old old old 46 dnop rb2 new data old data latency x t k
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 47 k cmd# page-mode dram read transfer (pipe-lined page-mode) latency set= 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# ad0-2 ad3-11 rb1 old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **c1 cs# ad0-ad2=low act drt dpd dnop dnop br br br br br br br br br dq0-15 trcd row row tcbf trasp trsh old old old old dram sram drt drt drt drt drt pcg dnop dnop **c2 **c3 **c4 **c5 **c6 tcbf tcbf tcbf tcbf tcbf c1 c2 c3 c4 c5 c6 q1 q1 q2 q2 q3 q4 q5 q6 q6 q6 tpc tpc tpc tpc tpc br br br br br pipe-lined page mode rb2 old data latency x t k c1 c2 c3 c4 c5 c6 latency x t k latency x t k latency x t k latency x t k latency x t k cas# dtd#
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# page-mode dram read transfer latency set= 2 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 rb old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **c1 cs# ad0-ad2=low act drt dpd dnop dnop br br br br br br br br br dq0-15 trcd row row tcbf trasp trsh old old old old dram sram drt drt drt drt drt pcg dnop dnop **c2 **c3 **c4 **c5 **c6 tcbf tcbf c1 c2 c6 q1 q1 q2 q2 q2 q2 q2 q6 q6 tpc tpc br br br br br old if next drt happens within the latency, new data does not transferred to rb. however this operation is not guaranteed. 48 rb1 old data tcbf tcbf tcbf tcbf tcbf tcbf c1 c2 c3 c4 c5 c6
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# page-mode dram read transfer latency set=3 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 rb1 old data sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low). **c1 cs# ad0-ad2=low act drt dpd dnop dnop br br br br br br br br br dq0-15 trcd row row tcbf trasp trsh old old old old dram sram drt drt pcg dnop dnop **c2 **c3 **c4 tcbf tcbf c1 c2 c4 q1 q1 q2 q2 q2 q2 q4 tpc tpc br br br br br old if next drt happens within the latency, new data does not transferred to rb. however this operation is not guaranteed. drt dnop dnop q1 old 49 rb2 old data latency x t k c1 c2 c4 c3 tcbf latency x t k latency x t k
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# page-mode dram read transfer latency set=4 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 rb old data **c1 cs# ad0-ad2=low act drt dpd dnop dnop br br br br br br br br br dq0-15 trcd row row tcbf trasp trsh old old old old dram sram drt pcg dnop dnop **c2 **c3 tcbf c1 c3 q1 q1 q1 q1 q1 q3 tpc br br br br br old if next drt happens within the latency, new data does not transferred to rb. however this operation is not guaranteed. drt dnop dnop q1 old dnop old 50 rb old data latency x t k c1 c3 latency x t k tcbf c2 sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1 new data[wb1(0-7)] old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd dpd dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trc trp trcd row row tras trwl d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 dram sram d0 wb2 c1 c2 c3 c4 c5 c6 c7 c0 c1 c2 c3 c4 c0 des dram write transfer 1 (wb1->wb2->dram) buffer write (din->wb1) please refer to next page in detail. 51 k cmd# sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# dram write transfer 1 (wb1->wb2->dram) buffer write (din->wb1) 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1[0] new data[from wb1(0-7)] old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd dpd dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trc trp trcd row row tras trwl d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 dram sram d0 wb2 [0-7] 0 0 des wb1 mask[0] wb1[1] 1 1 wb1 mask[1] wb1[2] wb1 mask[2] wb1[3] wb1 masl[3] wb1[4] wb1 mask[4] wb1[5] wb1 mask[5] wb1[6] wb1 mask[6] wb1[7] wb1 mask[7] 2 2 3 3 4 4 5 6 7 detail 52
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1 new data[wb1(0-7)] old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd dpd dpd sw sw sw sw sw sw sw bwt bwt sw sw sw sw dq0-15 trc trp trcd row row tras trwl dram sram wb2 sw dram write transfer 1 (wb1->wb2->dram) buffer write transfer (sram->wb1) please refer to next page in detail. old data new data next new data d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d0 53 sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# dram write transfer 1 (wb1->wb2->dram) buffer write transfer (sram->wb1) 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1[0] new data[from wb1(0-7)] old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd dpd dpd dq0-15 trc trp trcd row row tras trwl dram sram wb2 [0-7] 0 0 wb1 mask[0] wb1[1] 1 wb1 mask[1] wb1[2] wb1 mask[2] wb1[3] wb1 masl[3] wb1[4] wb1 mask[4] wb1[5] wb1 mask[5] wb1[6] wb1 mask[6] wb1[7] wb1 mask[7] 2 3 4 5 6 7 detail sw sw sw sw sw sw sw bwt bwt sw sw sw sw sw 1 2 3 4 5 6 7 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d0 54
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1 next data[wb1(0-1)] old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trp trcd row row trasp trwl d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 dram sram d0 wb2 c1 c2 c3 c4 c5 c6 c7 c0 c1 c2 c3 c4 c0 des page-mode dram write transfer 1 (wb1->wb2->dram) buffer write (din->wb1) please refer to next page in detail. dwt1 dnop tpc ad0-ad2=low **col new data[wb1(0-7)] 55 k cmd# sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# page-mode dram write transfer 1 (wb1->wb2->dram) buffer write (din->wb1) 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1[0] new data [from wb1(0-7)] old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trp trcd row row trasp 1 2 3 4 5 6 7 0 1 2 3 4 5 dram sram 0 wb2 [0-7] 0 0 des wb1 mask[0] wb1[1] 1 1 wb1 mask[1] wb1[2] wb1 mask[2] wb1[3] wb1 masl[3] wb1[4] wb1 mask[4] wb1[5] wb1 mask[5] wb1[6] wb1 mask[6] wb1[7] wb1 mask[7] 2 2 3 3 4 4 5 6 7 detail dnop dwt1 trwl tpc ad0-ad2=low **col next data[wb1(0-1)] 56
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1 new data[wb1(0-7)] old data **col cs# ad1-ad2=low pcg dpd dpd dpd dpd act dwt1r pcg dpd dnop dnop dpd dpd dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trc trp trcd row row tras trwl 1 2 3 4 5 6 7 0 1 2 3 4 5 dram sram 0 wb2 1 2 3 4 5 6 7 0 1 2 3 4 0 des dram write transfer 1&read (wb1->wb2->dram->rb) latency set=1 buffer write (din->wb1) rb1 old data new data[wb1(0-7)] tcbf tcbf ad0=high new data on rb appears as to latency set count. see drt timing chart. 57 rb2 old data new data[wb1(0-7)] tcbf latency x t k sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric k cmd# 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1 old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trp trcd row row trasp trwl 1 2 3 4 5 6 7 0 1 2 3 4 5 dram sram 0 wb2 1 2 3 4 5 6 7 0 1 2 3 4 0 des dram write transfer 2 (wb2->dram) dwt2 dnop tpc ad0,ad2=low **col new data[wb1(0-7)] ad1=high nochange 58 sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-2 ad3-11 wb1 old data **col cs# ad0-ad2=low pcg dpd dpd dpd dpd act dwt1 pcg dpd dnop dnop dpd bw bw bw bw bw bw bw bw bw bw bw bw bw dq0-15 trp trcd row row trasp trwl 1 2 3 4 5 6 7 0 1 2 3 4 5 dram sram 0 wb2 1 2 3 4 5 6 7 0 1 2 3 4 0 des dram write transfer2 & read (wb2->dram->rb1-> rb2) latency set=1 dwt2 dnop tpc ad2=low **col new data[wb1(0-7)] ad0,ad1=high nochange rb1 old data new data[wb1(0-7)] tcbf new data on rb appears as to latency set count. see drt timing chart. 59 rb1 old data new data[wb1(0-7)] latency x t k k cmd# sram operation can be freely performed. ** ad3-ad7 are column block addresses (ad8~ad11=low).
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 60 this page is left blank, so that the set command register timing diagram on the next spread can be seen conveniently.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric set command register (1) 2 3 4 5 6 7 8 9 10 11 12 13 14 1 ras# cas# dtd# ad0-11 *set command reg. cs# 61 cmd inhibit new command except for dnop,dpd des,spd and nop. row dpd dpd dpd dpd dpd dpd scr dpd dpd dpd act dnop dnop dnop k cmd#
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 62 * latency is the number of clock cycles required to transfer new data from the dram to the read buffer . therefore, it can be adjusted to the clock frequency of the system. (latency) x (tk) should meet tcbf min. timing requirement. k cmd# cs# ras# cas# dtd# ad0~11 command scr inhibit new read or write function during these 4 clocks. set command register(2) output modetransparent command latency 1 no operation set all wb1 xfer masks ad9 ad8 ad7 ad6 l l l l l l l l l ad5 l l h h ad4 l h l h ad3 l l h ad2 l h l ad1 l l l l l l l l l ad0 l h address input latency 2 latency 3 latency 4 output mode latched output mode registered sequential interleave bl=1 bl=2 bl=4 bl=8 l h l l l h h l h h l l l l l l l l l l l l l default default l l l ad10 ad11 l l l l default l l l l l l l l l l l l l l l l l l l default l l l l l l l l l l l l l l l l l l l
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 63 burst mode address initial address as2 bl as1 as0 y0 y1 y2 y3 y4 y5 y6 y7 sequential interleaved y0 y1 y2 y3 y4 y5 y6 y7 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 0 1 0 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 0 1 1 0 1 2 3 4 5 6 7 3 2 1 0 7 6 5 4 1 0 0 0 1 2 3 4 5 6 7 4 5 6 7 0 1 2 3 1 0 1 0 1 2 3 4 5 6 7 5 4 7 6 1 0 3 2 1 1 0 0 1 2 3 4 5 6 7 6 7 4 5 2 3 0 1 1 1 1 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 0 0 0 0 1 2 3 0 1 2 3 - 0 1 0 1 2 3 1 0 3 2 - 1 0 0 1 2 3 2 3 0 1 - 1 1 0 1 2 3 3 2 1 0 - - 0 0 1 0 1 - - 1 1 0 1 0 8 4 2 note: when sram command is executed more than burst length, the address repeats with the same sequence.
m5m4v16169dtp/rt-7,-8,-10,-15 16mcdram:16m(1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 64 dimension *1, *2 do not include mold flash. dimension *3 does not include tie - bar cut remain. note) 0.5+-0.1 (0.02+-0.004) detail a 23.49+-0.1 (0.925+-0.004) 0.65+-0.1 (0.026+-0.004) 0.3 +0.1 -0.05 1 35 36 *3 *2 (0.012 +0.004 -0.05 ) 0.1 (0.004) 70 a 0.125 +0.05 -0.02 (0.005 +0.02 -0.0008 ) unit : mm (inch) 70p3s package dimension 1 35 36 70 36 70 70p3s-l 70p3s-m

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